// Formal Verification Project
// Non-pipelined AES Unit

// Top-level Module

// 12/7/2011



module np_aes (	clk,
				rst,
				key,
				start,
				data_in,
				done,
				data_out);
				

input clk, rst;
input [0:127] key, data_in;
input start;

output [0:127] data_out;
output done;

wire [0:127] add_roundkey_o, sub_bytes_o, shift_rows_o, mix_columns_o;
wire [0:127] roundkey_0, roundkey_1, roundkey_2, roundkey_3, roundkey_4, roundkey_5, roundkey_6, roundkey_7, roundkey_8, roundkey_9, roundkey_10;
wire [0:127] current_key, state_out;

// declare modules
control ctrl ( 	.clk(clk),
				.rst(rst),
				.roundkey_0(roundkey_0),
				.roundkey_1(roundkey_1),
				.roundkey_2(roundkey_2),
				.roundkey_3(roundkey_3),
				.roundkey_4(roundkey_4),
				.roundkey_5(roundkey_5),
				.roundkey_6(roundkey_6),
				.roundkey_7(roundkey_7),
				.roundkey_8(roundkey_8),
				.roundkey_9(roundkey_9),
				.roundkey_10(roundkey_10),
				.current_key(current_key),
				.add_roundkey_o(add_roundkey_o),
				.sub_bytes_o(sub_bytes_o),
				.shift_rows_o(shift_rows_o),
				.mix_columns_o(mix_columns_o),
				.state_out(state_out),
				.data_in(data_in),
				.data_out(data_out),
				.done(done),
				.start(start)); 
				
				
key_expansion key_expand(	.key(key),
							.clk(clk),
							.rst(rst),
							.roundkey_0(roundkey_0),
							.roundkey_1(roundkey_1),
							.roundkey_2(roundkey_2),
							.roundkey_3(roundkey_3),
							.roundkey_4(roundkey_4),
							.roundkey_5(roundkey_5),
							.roundkey_6(roundkey_6),
							.roundkey_7(roundkey_7),
							.roundkey_8(roundkey_8),
							.roundkey_9(roundkey_9),
							.roundkey_10(roundkey_10));
							
add_roundkey add_key	(	.key(current_key),
							.state_in(state_out),
							.state_out(add_roundkey_o));
							
sub_bytes sBytes		(	.state_in(state_out),
							.state_out(sub_bytes_o));

shift_rows sRows		(	.state_in(state_out),
							.state_out(shift_rows_o));
							
mix_columns	mColumns	(	.state_in(state_out),
							.state_out(mix_columns_o));
							





endmodule